Formal verification engineer

A unique opportunity to take part in building an R&D team for a global company. We are seeking highly experienced and visionary formal verification engineer to contribute to the development of advanced AI connectivity architectures and help define the formal verification methodology from the ground up.

Responsibilities:

• Define and execute formal verification strategies and methodologies for complex SoCs, IPs, and networking architectures (Switches, NICs, SmartNICs).
• Develop, implement, and maintain formal verification environments and test plans from concept to production.
• Specify formal properties, assertions, and constraints using formal tools and SystemVerilog Assertions (SVA).
• Own the formal verification environment, including setup, maintenance, and integration with simulation-based flows.
• Collaborate closely with architecture, RTL, and design teams to identify corner cases, ensure functional correctness, and drive verification sign-off.
• Act as a key contributor in shaping the formal verification infrastructure and methodology of the new Israeli site.

Qualifications:

• B.Sc. in Computer Science or Computer Engineering.
• 5+ years of industry experience in formal verification.
• Proven experience with JasperGold, VC Formal, or similar formal verification tools.
• Demonstrated ownership and maintenance of formal verification environments.
• Strong analytical and problem-solving skills.
• Team player with excellent interpersonal and communication abilities.

Advantages:

• Experience as a verification engineer with practical knowledge of SystemVerilog and UVM methodology.
• Familiarity with networking architectures and IPs (Switches, NICs, SmartNICs).
• Experience integrating formal verification within broader project verification flows.