About Samsung Austin Semiconductor

Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At Samsung Austin Semiconductor, we are Innovating Today to Power the Devices of Tomorrow.

Come innovate with us!

Position Summary

The Design for Manufacturability (DFM) team is focused on incoming technology transfer, product optimization, new product introductions, yield improvement, process margin improvement and performance enhancement. As part of the Advanced Node Technology Development team, you will provide Design Verification for products in a high-volume production environment as well as optimization of newer products introduced exclusively at Samsung Austin Semiconductor.

Role and Responsibilities

Here’s What You’ll Be Responsible For:

• DFM engineer will collaborate with both internal teams and customer’s design teams to develop new offerings of devices, pcell and standard cell libraries.
• Leads projects related to design risk assessment of new product introductions, analyze yield to design correlations for yield improvement and other KPI improvements.
• Uses EDA software to analyze & design including extracting netlists, timing analysis, redundancy checks; consults and guide fabrication team on possibilities of margin improvements.
• Lead / participate in devising solutions/methodology to fix/avoid future vulnerabilities in the design.
• Write SVRF/tcl code for design risk assessment.
• Develops methodology and automation scripts using bash-shell, python, tcl etc.
• Communicates technical information to senior leadership outside of the department through presentations.
• Completes other duties as assigned.

Skills and Qualifications

Here's what you'll need:

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering. Other engineering domain e.g. Physics, Chemistry, Electrical Engineering, Chemical Engineering, Materials Science are ok as long as candidate has experience with design verification process.
• Experience with Cadence Virtuoso or other EDA experience in at least one of the following tools - Calibre, Yield Explorer, StarRC/xRC, ICC2 & TCAD.
• Working knowledge of the design-to-mask workflow (schematic, simulation, layout, physical verification, GDSII, mask).
• 300mm 16nm/14nm/10nm nodes (or below) wafer manufacturing technology experience is preferred.
• Strong scripting experience in one of the following - tcl, bash/shell or python.

Total Rewards

At Samsung Austin Semiconductor, base pay is just one part of our total compensation package. The base compensation for this role will depend on education, experience, skills, and location.

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE

Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance.

U.S. Export Control

This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Trade Secrets

By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

* Samsung Electronics America, Inc. and its subsidiaries are committed to Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.