ASIC Chip Lead and Design Engineer Job Description

You’ll play a key role in designing and delivering complex, custom ASICs from concept through silicon. This is a highly hands-on opportunity for an engineer who enjoys solving challenging digital design problems and working across the full ASIC/SoC development flow. You’ll collaborate closely with architecture, verification, physical design, applications, and business teams to turn demanding technical requirements into high-performance silicon while optimizing for power, performance, and area (PPA).

The ideal candidate is a high-aptitude engineer who is currently designing complex digital blocks and has strong, practical experience across the complete ASIC/SoC design lifecycle. Engineers with additional experience in radiation-hardened design, analog/mixed-signal circuits, EDA methodologies, or standard-cell library development will have an opportunity to apply and expand that expertise.

Essential Duties and Qualifications

• Chip Architecture and Development: Lead the architectural design of ASICs based on high-level requirements and block diagrams. Collaborate with system architects to define chip functionality, interfaces, and performance targets. Develop detailed specifications for the chip’s components.
• RTL Design and Synthesis: Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs. Optimize RTL code for area, power, and performance. Implement and verify complex digital blocks.
• Constraint Development: Develop timing constraints for the entire chip. Work closely with physical design teams to ensure successful place-and-route.
• RISC Processor Conformance: Constrain and verify RISC processors within the chip. Optimize processor performance and power efficiency.
• Physical Design Collaboration: Collaborate with physical design teams on floorplanning, placement, and routing. Address any design closure issues.
• Verification Support: Work with verification engineers to ensure functional correctness. Assist in creating testbenches and verifying the chip’s functionality.

Modern revision-control tools and best-practices in a collaborative, multi-site design community. Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g., sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting. Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.

Required Qualifications

• BSEE/MSEE or equivalent
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving skills and attention to detail.
• A strong background in RTL based digital IC design using Verilog/SystemVerilog.
• Proven track record of first-pass successes.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to mentor junior engineers.
• Experience with industry standard development tools and methodologies.