Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary:

The Design Implementation Methodology Engineer will work in Qualcomm's Adreno GPU Silicon team and will be responsible for developing and driving advanced design methodologies, infrastructure, and automation across synthesis, Static Timing Analysis (STA), power, and physical design using latest AI methodologies and framework.

The successful candidate should have a strong methodology mindset, programming and problem-solving skills, along with a good understanding of ASIC implementation. Candidates with exceptional technical aptitude and the ability to quickly develop implementation expertise will also be considered.

This is a hands-on role that goes beyond infrastructure/methodology development. The candidate will be expected to apply the infrastructure/methodologies to real design challenges and identify opportunities for measurable process, productivity, and Power, Performance and Area (PPA) improvements. The role will work closely with synthesis, STA, physical design, power, DFT teams to develop scalable methodologies and apply them across GPU designs.

The ideal candidate would have/able to demonstrate the following:

• Strong methodology mindset with excellent analytical and problem-solving skills
• Strong programming and scripting skills using Python, TCL, or similar languages
• Understanding of digital design, RTL synthesis, physical design, STA, power analysis, and ASIC implementation flows
• Ability to develop scalable design infrastructure, automation, and reusable methodologies
• Ability to apply infrastructure and analytics to identify PPA, design-flow, and engineering-productivity improvements
• Ability to investigate complex design problems and develop innovative, tool-agnostic methodology solutions
• Experience working with large volumes of design data and translating data into actionable engineering insights
• Excellent debug, communication, and collaboration skills
• Ability to work independently while collaborating across synthesis, STA, physical design, infrastructure, and AI teams
• Develop agentic framework workflows for engineering analysis and automation
• Drive targeted, EDA-tool-agnostic synthesis/physical design/STA methodology and PPA improvement initiatives

Preferred Skills:

• Hands-on experience with synthesis, STA and/or physical design implementation
• Experience with industry-standard EDA tools for synthesis, timing analysis, formal verification, power analysis, and physical design
• Experience developing reusable TCL/Python libraries and design-analysis infrastructure
• Experience with design-data analytics, dashboards, databases, and interfaces between design flows and data platforms
• Experience developing methodologies for clock structure/network analysis and PPA optimization
• Exposure to AI/LLM-based engineering applications, AI agents, or agentic workflows
• Experience interfacing EDA tools and design infrastructure with AI/LLM systems
• Ability to collaborate with core infrastructure and AI teams and integrate common capabilities into design methodologies
• Strong understanding of advanced-node VLSI design and implementation challenges

Minimum Skills:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Strong programming, scripting, analytical, and debugging skills
• Working knowledge of ASIC design and implementation concepts
• Experience or demonstrated ability to work across synthesis, STA, power, or physical-design domains
• Strong self-motivation with the ability to independently investigate and solve complex engineering problems

Minimum Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits:

$141,300.00 - $211,900.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.