Ethernet design verification engineer

Ethernet Design Verification Engineer Role Summary:

We are looking for an Ethernet DV Engineer to verify high-speed Ethernet IP and subsystems, ensuring full protocol compliance and functional correctness prior to tapeout.

Responsibilities:

• Develop and maintain UVM-based verification environments/testbenches for Ethernet MAC/PHY IP
• Write test plans and directed/random test cases covering Ethernet protocol layers (PCS, PMA, MAC)
• Verify compliance with IEEE 802.3 Ethernet standards across relevant speed grades (1G/10G/25G/50G/100G/400G)
• Perform functional coverage analysis and drive coverage closure
• Debug simulation failures and collaborate with design teams to root-cause issues
• Develop and reuse verification IP (VIP) for Ethernet interfaces
• Participate in regression testing and continuous integration for verification sign-off
• Support post-silicon validation and correlate simulation results with lab findings

Required Skills:

• SystemVerilog
• UVM
• Ethernet protocol knowledge (IEEE 802.3)
• Verification IP development
• Simulators (VCS/Questa/Xcelium)
• Scripting (Python/Perl/Tcl)

Experience:

5–16 years in DV/verification roles, Ethernet protocol experience strongly preferred